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← All SystemsSystem 03 / designReviewed Aug 29, 2026

Chip Design

Workload ideas pass through instruction sets, IP, verification, physical design, and software co-design before tape-out.

Understand the system

How it works

The chip is designed as a coupled system: compute, memory, I/O, packaging, yield, power, and software must close together before manufacturing begins.

Design dependencies

From design tools to tape-out

Select a capability to explore its role and connections.

Selected: EDA platforms

EDA platforms

Electronic-design-automation platforms coordinate specification, implementation, analysis, verification, and manufacturing handoff across complex chips.

Explore EDA platforms in Atlas

Documented connections

Selected documented dependencies. Arrows retain their Atlas direction; they do not represent quantities or a complete engineering process.

Chip design is the translation layer between an AI workload and manufacturable silicon. Architects choose data types, memory hierarchy, compute units, interconnect, security, and control; engineers integrate reusable IP, verify behavior, close timing and power, and produce the mask data a foundry can execute. Every late change collides with fixed package, compiler, process, and schedule constraints.

Workload shapes architecture

Training and inference reward different balances of arithmetic, precision, memory capacity, bandwidth, latency, and communications. Architecture begins by making those tradeoffs explicit, and NIST's current SoC work treats hardware/software co-design plus heterogeneous packaged components as one coupled architecture problem rather than sequential handoffs.

  • Tie data types to workload accuracy targets
  • Model memory movement before peak arithmetic
Supporting evidence · 3
  1. [1] NVIDIA specifies 141 GB of HBM3E capacity and 4.8 TB/s of memory bandwidth for the H200 accelerator.
  2. [2] PyTorch documents data, fully sharded data, tensor, and pipeline parallelism as complementary approaches for distributed model training.
  3. [3] NIST's current system-on-chip architecture work treats hardware/software co-design and heterogeneous packaged components as joint design considerations.

IP and instruction sets

Processor cores, memory controllers, SerDes, security blocks, and interface standards are often reused. Modular instruction sets widen the ecosystem, but CRS's revenue geography and the FTC's transaction remedy show that critical design tools and reusable IP remain concentrated enough to create policy and continuity risk.

  • Trace licensed and open IP separately
  • Expose compatibility as a supply-chain dependency
Supporting evidence · 4
  1. [1] The RISC-V instruction-set architecture is organized around a required base ISA plus optional standardized extensions.
  2. [2] PCI Express 6.0 doubles the raw data rate to 64 GT/s and supports up to 256 GB/s bidirectionally on an x16 link.
  3. [3] A Congressional Research Service synthesis reports that U.S.-headquartered companies accounted for 72 percent of worldwide electronic-design-automation and semiconductor-IP revenue in 2021.
  4. [4] The Federal Trade Commission's final order for the 35-billion-dollar Synopsys–Ansys transaction required divestitures in three specified software-tool markets to remedy competition concerns.

Verification is schedule insurance

Functional verification, emulation, formal methods, and physical signoff aim to find failures before masks and wafers make them extraordinarily expensive. NIST describes functional verification as more than half of new-chip design cost and its advanced-packaging program identifies the scale at which contemporary abstraction limits force full-chip designs into separately implemented blocks. A 2021 federal review's dated 7 nm and 5 nm cost estimates show the order of magnitude at risk, not a current universal design budget.

  • Verification loops close before tape-out
  • Design choices shape yield and test coverage
Supporting evidence · 6
  1. [1] SIA's high-level semiconductor value chain runs from research and development through chip design, front-end wafer fabrication, back-end assembly, test and packaging, and finally circuit-board integration into products.
  2. [2] Semiconductor design, equipment, materials, wafer fabrication, and assembly remain distributed across highly specialized regional clusters.
  3. [3] Leading-edge wafers pass through thousands of fabrication process steps over a period measured in weeks before packaging and test.
  4. [4] NIST's advanced-packaging research program identified roughly 100 million design instances as the point above which then-current EDA abstractions made full-chip implementation impractical, forcing designs to be partitioned into blocks.
  5. [5] A 2021 U.S. government supply-chain review reproduced industry estimates of 297.8 million dollars to design a 7-nanometer chip and 542.2 million dollars for a 5-nanometer chip.
  6. [6] NIST's current hardware-security program states that functional verification accounts for more than half of the cost of a new chip design.

Hardware and software co-design

Compiler support, kernels, libraries, frameworks, and collective-communication behavior determine whether new silicon becomes useful compute. Ecosystem maturity can outweigh isolated benchmark peaks.

  • Pair every accelerator with its software path
  • Measure portability costs and optimization depth
Supporting evidence · 2
  1. [1] CUDA and ROCm each combine programming models, runtimes, compilers, libraries, debugging tools, and hardware interfaces into an accelerator software stack.
  2. [2] PyTorch documents data, fully sharded data, tensor, and pipeline parallelism as complementary approaches for distributed model training.

Featured evidence

From workload to tape-outA design is a chain of testable commitments, not a single drawing.
  1. 01Workload

    Define useful work, latency, throughput, and memory behavior.

  2. 02Architecture

    Partition compute, memory, interconnect, control, and security.

  3. 03IP + process rules

    Bind reusable blocks to a manufacturable process and package.

  4. 04Verification

    Test logic, timing, power, interfaces, and physical constraints.

  5. 05Tape-out

    Release verified pattern data for masks and fabrication.

Key indicators

Key measures & constraints

  1. 01

    SIA's high-level semiconductor value chain runs from research and development through chip design, front-end wafer fabrication, back-end assembly, test and packaging, and finally circuit-board integration into products.

    Class
    fact
    Geography
    Global
    Period
    current industry overview
    Confidence
    high
    Trace evidence
  2. 02

    A Congressional Research Service synthesis reports that U.S.-headquartered companies accounted for 72 percent of worldwide electronic-design-automation and semiconductor-IP revenue in 2021.

    Class
    estimate
    Geography
    Global, by company headquarters
    Period
    2021
    Confidence
    medium
    Trace evidence
  3. 03

    NIST's advanced-packaging research program identified roughly 100 million design instances as the point above which then-current EDA abstractions made full-chip implementation impractical, forcing designs to be partitioned into blocks.

    Class
    estimate
    Geography
    Global
    Period
    2024 program assessment
    Confidence
    medium
    Trace evidence
  4. 04

    The Federal Trade Commission's final order for the 35-billion-dollar Synopsys–Ansys transaction required divestitures in three specified software-tool markets to remedy competition concerns.

    Class
    fact
    Geography
    United States with global market implications
    Period
    October 2025 final order
    Confidence
    high
    Trace evidence
  5. 05

    CUDA and ROCm each combine programming models, runtimes, compilers, libraries, debugging tools, and hardware interfaces into an accelerator software stack.

    Class
    fact
    Geography
    Global
    Period
    2026 documentation
    Confidence
    high
    Trace evidence

System map

Connections across the system

Explore inputs, outputs, and shared capabilities in the Atlas. Open the register for every documented relationship.

Across the system boundary Selected documented relationships · arrows follow the Atlas

Enters this system 1

  1. AI storage→ Runtime & frameworksTrace relationship

Leaves this system 4

  1. Photomasks← Accelerator architectureTrace relationship
  2. AI rack system← Runtime & frameworksTrace relationship
System 03Chip Design10 internal relationships

Shared capabilities can belong to more than one System. These links carry materials, energy, information, capital, or permissions; they describe dependencies, not quantities or a complete process model.

Explore 8 capabilities and operating boundaries
Atlas nodes / 8
All documented relationships · 15
  1. criticaloutput
    Accelerator architecturePhotomasks

    Verified physical design is converted into mask pattern data.

    Trace relationship
    Supporting evidence · 2
    1. [1] SIA's high-level semiconductor value chain runs from research and development through chip design, front-end wafer fabrication, back-end assembly, test and packaging, and finally circuit-board integration into products.
    2. [2] ASML specifies a 0.55 numerical aperture and 8 nm resolution for the TWINSCAN EXE:5000 High-NA EUV system.
  2. criticaloutput
    Runtime & frameworksAI rack system

    Drivers, kernels, frameworks, and scheduling convert hardware into useful work.

    Trace relationship
    Supporting evidence · 2
    1. [1] CUDA and ROCm each combine programming models, runtimes, compilers, libraries, debugging tools, and hardware interfaces into an accelerator software stack.
    2. [2] PyTorch documents data, fully sharded data, tensor, and pipeline parallelism as complementary approaches for distributed model training.
  3. criticalinternal
    EDA platformsVerification & emulation

    EDA platforms provide the simulation, analysis, and emulation flow used to close verification.

    Trace relationship
    Supporting evidence · 2
    1. [1] NIST's current hardware-security program states that functional verification accounts for more than half of the cost of a new chip design.
    2. [2] The Federal Trade Commission's final order for the 35-billion-dollar Synopsys–Ansys transaction required divestitures in three specified software-tool markets to remedy competition concerns.
  4. criticalinternal
    Verification & emulationPDKs & physical design

    Verified design intent advances into process-specific implementation and signoff.

    Trace relationship
    Supporting evidence · 2
    1. [1] NIST's current hardware-security program states that functional verification accounts for more than half of the cost of a new chip design.
    2. [2] NIST's advanced-packaging research program identified roughly 100 million design instances as the point above which then-current EDA abstractions made full-chip implementation impractical, forcing designs to be partitioned into blocks.
  5. criticalinternal
    PDKs & physical designTape-out & mask handoff

    Foundry rules and physical signoff produce the release representation used for tape-out.

    Trace relationship
    Supporting evidence · 2
    1. [1] A 2021 U.S. government supply-chain review reproduced industry estimates of 297.8 million dollars to design a 7-nanometer chip and 542.2 million dollars for a 5-nanometer chip.
    2. [2] NIST's advanced-packaging research program identified roughly 100 million design instances as the point above which then-current EDA abstractions made full-chip implementation impractical, forcing designs to be partitioned into blocks.
  6. criticaloutput
    Tape-out & mask handoffPhotomasks

    Tape-out data drives preparation of the mask set for the selected process.

    Trace relationship
    Supporting evidence · 2
    1. [1] SIA's high-level semiconductor value chain runs from research and development through chip design, front-end wafer fabrication, back-end assembly, test and packaging, and finally circuit-board integration into products.
    2. [2] ASML specifies a 0.55 numerical aperture and 8 nm resolution for the TWINSCAN EXE:5000 High-NA EUV system.
  7. importantinternal
    Runtime & frameworksAccelerator architecture

    Software capabilities and workload behavior feed back into hardware design.

    Trace relationship
    Supporting evidence · 1
    1. [1] CUDA and ROCm each combine programming models, runtimes, compilers, libraries, debugging tools, and hardware interfaces into an accelerator software stack.
  8. importantoutput
    Runtime & frameworksScale-out network

    Parallelism and collective libraries shape network traffic and topology needs.

    Trace relationship
    Supporting evidence · 1
    1. [1] PyTorch documents data, fully sharded data, tensor, and pipeline parallelism as complementary approaches for distributed model training.
  9. importantinput
    AI storageRuntime & frameworks

    Datasets and checkpoints feed training and recovery workflows.

    Trace relationship
    Supporting evidence · 1
    1. [1] Industry presenters working through SNIA describe AI storage as needing to sustain dataset ingest while absorbing checkpoints and supporting recovery without leaving accelerators idle.
  10. importantinternal
    EDA platformsAccelerator architecture

    EDA platforms supplies a distinct operating capability within its broader Atlas system.

    Trace relationship
    Supporting evidence · 2
    1. [1] A Congressional Research Service synthesis reports that U.S.-headquartered companies accounted for 72 percent of worldwide electronic-design-automation and semiconductor-IP revenue in 2021.
    2. [2] The Federal Trade Commission's final order for the 35-billion-dollar Synopsys–Ansys transaction required divestitures in three specified software-tool markets to remedy competition concerns.
  11. importantinternal
    Verification & emulationAccelerator architecture

    Verification & emulation supplies a distinct operating capability within its broader Atlas system.

    Trace relationship
    Supporting evidence · 2
    1. [1] NIST's current hardware-security program states that functional verification accounts for more than half of the cost of a new chip design.
    2. [2] A 2021 U.S. government supply-chain review reproduced industry estimates of 297.8 million dollars to design a 7-nanometer chip and 542.2 million dollars for a 5-nanometer chip.
  12. importantinternal
    PDKs & physical designAccelerator architecture

    PDKs & physical design supplies a distinct operating capability within its broader Atlas system.

    Trace relationship
    Supporting evidence · 2
    1. [1] NIST's advanced-packaging research program identified roughly 100 million design instances as the point above which then-current EDA abstractions made full-chip implementation impractical, forcing designs to be partitioned into blocks.
    2. [2] NIST's current system-on-chip architecture work treats hardware/software co-design and heterogeneous packaged components as joint design considerations.
  13. importantinternal
    Tape-out & mask handoffAccelerator architecture

    Tape-out & mask handoff supplies a distinct operating capability within its broader Atlas system.

    Trace relationship
    Supporting evidence · 2
    1. [1] A 2021 U.S. government supply-chain review reproduced industry estimates of 297.8 million dollars to design a 7-nanometer chip and 542.2 million dollars for a 5-nanometer chip.
    2. [2] SIA's high-level semiconductor value chain runs from research and development through chip design, front-end wafer fabrication, back-end assembly, test and packaging, and finally circuit-board integration into products.
  14. importantinternal
    Hardware/software co-designAccelerator architecture

    Hardware/software co-design supplies a distinct operating capability within its broader Atlas system.

    Trace relationship
    Supporting evidence · 2
    1. [1] NIST's current system-on-chip architecture work treats hardware/software co-design and heterogeneous packaged components as joint design considerations.
    2. [2] CUDA and ROCm each combine programming models, runtimes, compilers, libraries, debugging tools, and hardware interfaces into an accelerator software stack.
  15. enablinginternal
    ISA & reusable IPAccelerator architecture

    Instruction sets and reusable IP constrain and accelerate architecture design.

    Trace relationship
    Supporting evidence · 1
    1. [1] The RISC-V instruction-set architecture is organized around a required base ISA plus optional standardized extensions.

Named companies + institutions

Organizations & their roles

  1. principal · standards body

    RISC-V International

    RISC-V International Association

    Standards organization maintaining the open RISC-V instruction-set architecture specifications.

    Roles, locations & evidence
    Role
    standards setter
    Products / service
    RISC-V instruction-set standards
    Documented activity
    World
    Headquarters
    Not cataloged
    Why this organization belongs in the System
    • ISA & reusable IP

      Primary-source evidence connects this institution to risc-v instruction-set standards in the specified Atlas capability.

  2. material · public company

    Arista Networks

    Arista Networks, Inc.

    Cloud-networking company supplying high-speed switching systems, routing platforms, and network software.

    Roles, locations & evidence
    Role
    supplier
    Products / service
    Network operating software
    Documented activity
    World
    Headquarters
    United States
    Why this organization belongs in the System
    • Runtime & frameworks

      Arista Networks's filing-backed operating portfolio includes network operating software; no subregional operating place is asserted, and headquarters is not used as a proxy. Representative status does not imply market rank.

  3. material · public company

    Cisco

    Cisco Systems, Inc.

    Networking and security company supplying switching, routing, optical, observability, and data-center infrastructure.

    Roles, locations & evidence
    Role
    supplier
    Products / service
    Network operating and observability software
    Documented activity
    World
    Headquarters
    United States
    Why this organization belongs in the System
    • Runtime & frameworks

      Cisco's filing-backed operating portfolio includes network operating and observability software; no subregional operating place is asserted, and headquarters is not used as a proxy. Representative status does not imply market rank.

  4. material · nonprofit

    PyTorch Foundation

    Open-source foundation supporting the PyTorch machine-learning framework and distributed-computing ecosystem.

    Roles, locations & evidence
    Role
    standards setter
    Products / service
    distributed machine-learning software
    Documented activity
    World
    Headquarters
    Not cataloged
    Why this organization belongs in the System
    • Runtime & frameworks

      Primary-source evidence connects this institution to distributed machine-learning software in the specified Atlas capability.

All other organizations · 6
  1. representative · public company

    Alphabet

    Alphabet Inc.

    Technology holding company whose Google businesses procure and operate global AI compute and cloud infrastructure.

    Roles, locations & evidence
    Role
    designer
    Products / service
    Custom accelerators and AI software co-design
    Documented activity
    World
    Headquarters
    United States
    Why this organization belongs in the System
    • Hardware/software co-design

      Alphabet's filing-backed operating portfolio includes custom accelerators and ai software co-design; no subregional operating place is asserted, and headquarters is not used as a proxy. Representative status does not imply market rank.

  2. representative · public company

    AMD

    Advanced Micro Devices, Inc.

    Semiconductor company that designs CPUs, GPUs, adaptive computing products, and associated AI software.

    Roles, locations & evidence
    Role
    supplier
    Products / service
    ROCm software platform
    Documented activity
    World
    Headquarters
    United States
    Why this organization belongs in the System
    • Runtime & frameworks

      AMD's filing-backed operating portfolio includes rocm software platform; no subregional operating place is asserted, and headquarters is not used as a proxy. Representative status does not imply market rank.

  3. representative · public company

    Arm

    Arm Holdings plc

    Semiconductor intellectual-property company licensing CPU architectures, cores, subsystems, and software tools.

    Roles, locations & evidence
    Role
    supplier
    Products / service
    Compute subsystems and design enablement · CPU architecture and reusable processor IP
    Documented activity
    World
    Headquarters
    United Kingdom
    Why this organization belongs in the System
    • Accelerator architecture

      Arm's filing-backed operating portfolio includes compute subsystems and design enablement; no subregional operating place is asserted, and headquarters is not used as a proxy. Representative status does not imply market rank.

    • ISA & reusable IP

      Arm's filing-backed operating portfolio includes cpu architecture and reusable processor ip; no subregional operating place is asserted, and headquarters is not used as a proxy. Representative status does not imply market rank.

  4. representative · public company

    Cadence

    Cadence Design Systems, Inc.

    Electronic-design-automation company supplying implementation, verification, emulation, and systems-analysis tools.

    Roles, locations & evidence
    Role
    supplier
    Products / service
    EDA software · Physical implementation and signoff tools · Verification and emulation platforms
    Documented activity
    World
    Headquarters
    United States
    Why this organization belongs in the System
    • EDA platforms

      Cadence's filing-backed operating portfolio includes eda software; no subregional operating place is asserted, and headquarters is not used as a proxy. Representative status does not imply market rank.

    • PDKs & physical design

      Cadence's filing-backed operating portfolio includes physical implementation and signoff tools; no subregional operating place is asserted, and headquarters is not used as a proxy. Representative status does not imply market rank.

    • Verification & emulation

      Cadence's filing-backed operating portfolio includes verification and emulation platforms; no subregional operating place is asserted, and headquarters is not used as a proxy. Representative status does not imply market rank.

  5. representative · public company

    NVIDIA

    NVIDIA Corporation

    Computing-platform company that designs AI accelerators, interconnects, systems, and the software stack that operates them.

    Roles, locations & evidence
    Role
    supplier
    Products / service
    CUDA software platform
    Documented activity
    World
    Headquarters
    United States
    Why this organization belongs in the System
    • Runtime & frameworks

      NVIDIA's filing-backed operating portfolio includes cuda software platform; no subregional operating place is asserted, and headquarters is not used as a proxy. Representative status does not imply market rank.

  6. representative · public company

    Synopsys

    Synopsys, Inc.

    Electronic-design-automation and semiconductor-IP company supporting chip implementation, verification, and signoff.

    Roles, locations & evidence
    Role
    supplier
    Products / service
    EDA software and semiconductor IP · Reusable semiconductor IP · Verification and emulation tools
    Documented activity
    World
    Headquarters
    United States
    Why this organization belongs in the System
    • EDA platforms

      Synopsys's filing-backed operating portfolio includes eda software and semiconductor ip; no subregional operating place is asserted, and headquarters is not used as a proxy. Representative status does not imply market rank.

    • ISA & reusable IP

      Synopsys's filing-backed operating portfolio includes reusable semiconductor ip; no subregional operating place is asserted, and headquarters is not used as a proxy. Representative status does not imply market rank.

    • Verification & emulation

      Synopsys's filing-backed operating portfolio includes verification and emulation tools; no subregional operating place is asserted, and headquarters is not used as a proxy. Representative status does not imply market rank.

Read this System in the field guide

Continue in the Volumes

Start with three selected readings, or explore the complete reading list.

Start here
  1. 01
    Volume II · PrecisionWorkload becomes architecture
  2. 02
    Volume II · PrecisionChiplets, IP, and process rules
  3. 03
    Volume II · PrecisionVerification and tape-out
Complete reading list
Volume II

Precision

4 spreads
  1. II · 01Workload becomes architecture
  2. II · 02Compute architectures
  3. II · 03Chiplets, IP, and process rules
  4. II · 04Verification and tape-out
Related cross-System reading · 8 spreads

Evidence & review

currentEvidence health24 active claims · next review Oct 13, 2026
Active claims
24
Sources
32
High volatility
1
Next review
Oct 13, 2026
Due soon
0
Overdue
0
Superseded
0
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Evidence, in context.

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